In many semiconductor devices such as embedded processors, systems-on-a-chip (SOC), or other computer systems or consumer electronic devices, on-chip busses are becoming faster and wider with many associated register queues and related logic in attached unit interfaces. Split transaction capabilities on these busses have added significant depth to these queues. This is leading to a situation where on-chip busses and their associated interfaces will become a significant portion of overall system power, particularly in SOC designs.
In prior systems, power management may include simply reducing clock frequency for portions of the system (e.g., host processor), stopping clocks to unused logic units, or reducing clock frequency for the entire system, including busses. Another technique that is used is to throttle the clock off and on rather than slowing the clock down. These prior systems do not provide throttling of shared system resources such as backbone busses based on bandwidth demands and do not provide adjustments to arbitration configuration to provide sustained and stable bandwidth allocations despite aggregate bandwidth reductions.